This invention relates generally to electronic devices, and more specifically to thin profile and small footprint packages and methods of assembly.
The handheld consumer products market is aggressive in the miniaturization of portable electronics. Driven primarily by the cellular phone and digital assistant markets, manufacturers of these devices are challenged by ever shrinking formats and the demand for more PC-like functionality. This challenge asserts pressure on surface mount component manufacturers to design their products to command the smallest area possible. By doing so, this allows portable electronics designers to incorporate additional functions within a device without increasing the overall product size. Leadless packages having one or more exposed integrated circuit terminations are one type of package structure that provides semiconductor manufacturers with an ability to significantly reduce the size of a surface mounted device. Such packages include Quad Flat Non-leaded (QFN) style designs with exposed terminations as well as the DirectFET™ package by International Rectifier Corporation.
Several manufacturing problems exist with current surface mount type packages with exposed terminations. For example, during solder attach and/or solder reflow steps, the semiconductor die tends to move, thus affecting the overall orientation of bonding areas (e.g., source, emitter, gate, or base electrode bonding areas). This detrimentally impacts the alignment of the surface mount device when it is attached to a printed circuit board or a next level of assembly.
Additionally, typical surface mount package manufacturing methods utilize single cavity molding processes. Such processes use mold cavities with mold compound runners and gate regions, which tend to waste mold compound material during manufacturing. Also, single cavity molding processes require manufactures to use lead frames with excess lead frame material, which is later removed and discarded as waste. Such waste materials increase manufacturing costs and can be a detriment to the environment.
U.S. Patent Application Publication 2004/0108580 dated Jun. 10, 2004 by applicants Kim Hwee Tan et al., describes a package structure that uses a single flip chip solder bumped semiconductor connected to a recessed lead frame. Tan further describes a fully encapsulated structure as well as a version with an exposed die back side for thermal enhancement. Tan uses a grinding process to remove encapsulating material to provide the exposed die back side. One disadvantage of Tan's structure is that it uses a flip-chip interconnect scheme. Such schemes require under bump metallurgy (UBM) and solder bump plating processes, which add to chip manufacturing costs. UBM refers to the layers of metallization that provide an interface between bond pads located on the chips and the solder bump, and typically consists of three separate layers. In addition, the solder bumps can cause stress issues with the chip and/or package structure, which can lead to quality and reliability issues. Additionally, Tan's grinding process can damage the semiconductor chip and/or the package, which can also lead to quality and reliability issues.
Accordingly, a need exists for an improved electronic package structure and method that addresses, among other things, die alignment issues, and that reduces materials waste. Additionally, it would be advantageous to have a structure and method that supports multiple chip layout designs, flexible interconnect or routing schemes, and chips with solderable, bumpless, or non-flip chip top metal structures.